Current commercial tools, such as Synopsys' Custom Designer and Cadence's Virtuoso, support design of standard cells for integrated circuits (“ICs”). These tools provide an interactive design system in which each polygon is placed individually for the cell based on a set of design rules. Design rules for ICs are well known in the electronic circuit design automation (“EDA”) industry. Design rules are specific to a particular semiconductor manufacturing process. A set of design rules identifies various geometric and connectivity restrictions to ensure sufficient margins exist in the design of the IC to account for variability in the semiconductor manufacturing process. One use for design rules relates to preventing illegal combinations of polygons in a particular design.
But design rules permit many relationships among polygons or other IC elements, allowing for numerous patterns that typically cannot be verified for manufacturability. A better solution involves a template-based approach utilizing a “templatyzer” tool as described in the related U.S. Pat. No. 9,870,441. A template-based approach to standard cell design minimizes the number of patterns to be verified for manufacturability. A templatyzer tool applies a “golden library” of standard cells to implement a template approach to standard cell-based IC design.
The template-based approach takes a proactive methodology for authorizing acceptable patterns, thereby obtaining a valid pattern corresponding to a physical pattern that can be manufactured in a resulting semiconductor device. Instead of relying on an elaborate set of design rules used in prior art systems (such as e.g., Synopsys' Custom Designer and Cadence's Virtuoso), using template-based design, sanctioned patterns can be designated by their presence in the golden library, which may consist of a small (e.g., 15-25) set of standard cells-referred to as “golden cells”—that contain allowable patterns for the IC design. The set of allowed patterns makes up the template architecture.
Various types of patterns are employed, for example:                a. Route—width+position of long axis;        b. Line end—width+position of short end of rectangle;        c. Size—height+width;        d. Position—center x, y coordinates;        e. Extension—distance from via to edge of enclosing shape;        f. Enclosure—three shortest distances from via to enclosing shape; and        g. X, Y—properties: center position+height/width (which can be a combination of “size” and “position” types above).        